Industry · Semiconductors
Semiconductors & microelectronics
At advanced nodes, a few defects per square centimeter and a few millivolts of unplanned threshold shift decide whether a wafer is worth the wire. We build the calibrated simulation and optimization stack that closes the gap between what TCAD predicts and what silicon actually does.
01The problem
Consider Intel's 18A, the industry's first node to pair gate-all-around RibbonFET transistors with PowerVia backside power delivery. Its yield ramp has been a public, closely watched challenge, and at these dimensions device behavior diverges from TCAD predictions, so recalibrating process and device models to measured silicon is slow and costs experimental wafers. The price of guessing wrong is steep: a leading-edge mask set can cost more than 10 million dollars at 7nm and approaches roughly 40 million at 3nm, across more than 60 unique lithography layers, all committed before a single wafer is measured. Every node vendor faces the same wall: yield loss and process variation that classical compact models and hand-tuned simulation no longer capture.
02How we solve it
Calibrate simulation to silicon, then co-optimize.
Agentriq keeps ML-accelerated TCAD and variation-aware compact models locked to real wafer data, then searches the design-technology space for robust, high-yield windows.
Design-Technology Co-Optimization (DTCO)
Co-tunes process choices and design rules against power, performance, area, and yield in one loop instead of throwing designs over the wall to the fab.
ML-accelerated TCAD calibration and surrogates
Learns fast surrogates for Sentaurus process and device simulation and fits their parameters to measured wafers, cutting calibration turnaround and the need for expensive test lots.
Variation-aware TCAD-to-SPICE compact models
Propagates work-function variation, line-edge roughness, and gate-edge roughness into BSIM-CMG statistical compact models for Monte Carlo yield estimation.
Surrogate-based yield and robust optimization
Uses Bayesian optimization and polynomial-chaos surrogates to locate robust, high-yield operating windows in a fraction of the expensive solver calls.
03What it produces
Yield windows in fewer runs.
A calibrated, variation-aware model stack that reproduces process-variation effects to within about one percent of stochastic TCAD and reaches calibrated results roughly an order of magnitude faster than manual tuning, so DTCO decisions rest on silicon-grounded numbers.
04The agentic loop
From wafer data to verified decision.
Agentriq wraps calibration, simulation, and optimization in a closed agent loop that pulls fresh silicon and metrology, re-fits the models, proposes the next split, and only accepts what it can verify.
- 01Ingest process splits, metrology, and electrical test data, and set the target power, performance, area, and yield window.
- 02Retrain ML-accelerated TCAD surrogates and refit variation-aware compact models against the latest measured silicon.
- 03Search the design-technology space with Bayesian optimization and polynomial-chaos yield estimates to propose robust candidate splits.
- 04Verify candidates against held-out wafers and stochastic TCAD, and when one misses, root-cause it with Agentic RAG over process notes, prior splits, and the literature.
- 05An LLM judge scores the recommendation on yield, PPA, and confidence, then writes the accepted split and model versions back to the record.
05Tooling
Simulation, solvers & frameworks.
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